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ORCIDIntegration, Volume 10
Volume 10, Number 1, September 1990
- Lambert Spaanenburg:
Editorial. 1 - Ted C. Yang, Che W. Chiou:
Universal syndrome-testable design of programmable logic arrays. 3-8 - Ted C. Yang, Che W. Chiou:
Testable PLA design with minimal overheads. 9-18 - Kuo-Feng Liao, D. T. Lee, Majid Sarrafzadeh:
Planar subset of multi-terminal nets. 19-37 - Youngtak Kim, Myunghwan Kim:
A stepwise-overlapped parallel simulated annealing algorithm. 39-54 - Pei-Yung Hsiao, H. F. Steven Chen, Wu-Shiung Feng:
A new control strategy for an artificial intelligence approach to VLSI layout compaction. 55-70 - Yannis Papananos:
A new wiring architectUre for parallel processing applications. 71-88 - Wing K. Luk, Alvar A. Dean, John W. Mathews:
Partitioning and floor-planning for data-path chip (microprocessor) layout. 89-108
Volume 10, Number 2, January 1991
- Michael Payer:
Partitioning and ordering of CMOS circuits for switch level analysis. 113-141 - Georg Pelz, Volker Meyer zu Bexten:
Efficient fracturing of all angle shaped VLSI mask pattern data. 143-154 - Lucas S. Heusler, Wolfgang Fichtner:
Transistor sizing for large combinational digital CMOS circuits. 155-168 - Francesco Curatelli:
Region definition and ordering for macrocells with unconstrained placement. 169-184 - H. Y. Chen, Sung-Mo Kang:
iCOACH: A circuit optimization aid for CMOS high-performance circuits. 185-212
Volume 10, Number 3, February 1991
- Lambert Spaanenburg:
Editorial. i - Christian Piguet, Evert Dijkstra:
Design methodologies and CAD tools. 219-250 - H. J. Kappen:
An efficient heuristic for standard-cell placement. 251-269 - David C. Ku, Giovanni De Micheli:
Optimal synthesis of control logic from behavioral specifications. 271-298 - Emile H. L. Aarts, F. M. J. de Bont, Jan H. M. Korst, J. M. J. Rongen:
An efficient macro-cell placement algorithm. 299-317 - Takako Matoba, Kuo Chi Lee, Gary E. Herman, William H. Mansfield Jr.:
A rapid turnaround design of a high speed VLSI search processor. 319-337
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